This invention relates to an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit from damaging by electrostatic discharge, and more particularly to an ESD protection circuit with silicon controlled rectifier (SCR) characteristics to improve its trigger current for avoiding undesired latch-up phenomena.
Electrostatic discharge (ESD), which is due to the accumulated charge of human bodies and machines discharged, is a serious issue for integrated circuit. The electrostatic discharges would damage the integrated circuit, due to an instant over-high voltage. For avoiding the integrated circuit from damaging by electrostatic discharges, ESD protection circuits are usually set between the pins of integrated circuit and inputs pads. Generally, the trigger voltage and holding voltage of ESD protection circuit can decide its performance. The lower trigger voltage and holding voltage are the better performance of ESD protection circuit is. Thus, many designs of ESD protection circuits are employed to provide lower trigger voltages and holding voltages.
FIG. 1 shows a silicon controlled rectifier (SCR), one of the conventional ESD protection circuit, which is issued as the U.S. Pat. No. 5,012,317. A silicon controlled rectifier 2 is interposed between an input pad 22 and circuit structure 24. The silicon controlled rectifier 2 is fabricated in a silicon based substrate 10, which is doped with P-type dopant. An N-well 12 is formed in the substrate 10, in which a first N-type doped region 14 and second P-type doped region 16 with higher concentrations than the concentration of the N-well 12 are formed therein. A third N-type doped region 18 and fourth P-type doped region 20 are formed in the: substrate 10, and connected to a reference potential. When the electrostatic discharge inputted from the input pad 22 is higher than the trigger voltage, the electrostatic discharge would be bypassed via the first N-type doped region 14 and second P-type doped region 16 through the silicon controlled rectifier 21 to the reference potential via the third N-type doped region 18 and fourth P-type doped region 20, thereby protecting the circuit structure 24 from damage.
FIG. 2 shows an equivalent circuit schematic of the silicon controlled rectifier 2 shown in FIG. 1. The resistor 13 is provided by the first N-type doped region 14 and lightly doped N-well 12 and the resistor 15 is provided by the substrate 10 and fourth P-type doped region 20, in which the N-well 12 and substrate 10 contribute the main portions of the resistor 13 and 15, respectively. The N-well 12, substrate 10, and third N-type doped region 18 serve as the collector, base, and emitter of the npn bipolar transistor 20, respectively. Similarly, the second P-type doped region 16, N-well 12, and substrate 10 serve as the emitter, base, collector of the pnp bipolar transistor 22, respectively. The equivalent circuit is connected to a reference potential, i.e. ground, for bypassing the electrostatic discharge inputted from the input pad 22.
When a normal operating voltage of ,the circuit structure 24 is inputted from the input pad 22, the junction between the N-well 12 and substrate 10 is reverse-biased. Namely, the collector-base junctions of bipolar transistors 20 and 22 are reverse-biased. Although, the emitter-base junction of bipolar transistors 20 and 22 are forward-biased, very little current is conducted by the circuit because of the reverse-biased junction between the N-well 12 and substrate 10. When the input pad 22 emits an electrostatic discharge higher than 70 volts, an avalanche occurs at the junction between the N-well 12 and substrate 10. The npn bipolar transistor 20 and pnp bipolar transistor 22 are turned on concurrently, thereby bypassing the electrostatic discharge to the reference potential. Meanwhile, that the bipolar transistors 20 and 22 providing base bias for each other allows the circuit remaining conductive in a much lower holding voltage than the avalanche voltage, until the voltage of electrostatic discharge approaches zero. Therefore, the circuit, namely silicon controlled rectifier, provides a good protection performance for the circuit structure 24, because of its low holding voltage.
Although the silicon controlled rectifier has a low holding voltage, it also needs a high trigger voltage, approximately 70-80 volts as the avalanche voltage between N-well and P-substrate, thus degrading the sensitivity to the electrostatic discharge. For lowering the trigger voltage, many patents modified the silicon controlled rectifier, such as U.S. Pat. No. 4,939,616 and U.S. Pat. No. 5,465,189, are proposed to solve this problem and reach a great success.
G. Notermans, xe2x80x9cOn the use of n-well resistors in ESD protectionsxe2x80x9d Micro electronics Reliability 38 (1998) pp. 1741-1748 reports that a multiple-finger chip has difficulty to activate all the ESD protection device connected with its multiple fingers. Due to the high electrostatic current for a single ESD protection device, the ESD protection device might be triggered before it reaches the trigger voltage. The undesired trigger would seriously cause the ESD protection device a latch-up. Since the silicon controlled rectifier has many advantages, there is a huge need to modify the silicon controlled rectifier as an ESD protection circuit with a higher trigger current for avoiding undesired trigger and latch-up.
This invention discloses an ESD protection circuit for bypassing electrostatic discharges from an input pad to a reference potential. A first N-well, which has a second N-type doped region and third P-type doped region, is formed in a P-type substrate. A fourth N-type doped region and fifth doped region are formed adjacent to the first N-well in the substrate. A first conducting structure is formed on the second N-type doped region and connected to an anode. A second conducting structure is formed on the fourth N-type doped region and fifth P-type doped region and connected to a reference potential. When electrostatic discharge flows from the input pad into the ESD protection circuit, the npn bipolar transistor, which includes the first N-type well, P-type substrate, and fourth N-type region, is turned on first. While the flowing current increased, the floated pnp bipolar transistor, which includes the third P-type region, first N-well, and P-type substrate, is subsequently activated, thereby increasing the trigger current of this ESD protection circuit.